1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a MOS transistor.
2. Background of the Related Art
FIGS. 1a to 1h illustrate cross sectional views showing the steps of a related art method for fabricating a MOS transistor having dual gates. FIG. 2 shows a related art ion injection state.
As shown in FIG. 1a, P type impurity ions and N type impurity ions are respectively injected into isolated regions of a semiconductor substrate 1 to form a P type well 2 and an N type well 3. As shown in FIG. 1b, a gate oxide film 4 is formed on an active region and a polysilicon layer 5 is deposited on the gate oxide film 4. The polysilicon layer 5 is deposited at approx. 610.degree. C. using SiH.sub.4 gas, for the purpose of forming small grain sizes. As shown in FIG. 1c, the polysilicon layer 5 and the gate oxide film 4 are selectively removed, to form a gate electrode 5a and a gate oxide film portion 4a on each of the P type well 2 and the N type well 3.
As shown in FIG. 1d, a first photoresist film 6 is formed on the substrate 1 such that it covers the N type well 3, but not the P type well 2. Then, N type arsenic (As) impurity ions are lightly injected into the exposed surface of the P type well 2. As shown in FIG. 1e, the first photoresist film 6 is removed. Next, a second photoresist film 7 is formed on the substrate 1 such that it covers the P type well 2, but not the N type well 3. Then, P type boron (B.sup.+) impurity ions are lightly injected into the exposed surface of the N type well 3.
As shown in FIG. 1f, the second photoresist film 7 is removed, and an oxide film is deposited by chemical vapor deposition (CVD) on the entire upper surface. The oxide film is subjected to anisotropic etching to form oxide film sidewalls 8 at the sides of each gate electrode 5a. Then, nitrogen ions are injected into the gate oxide film 4a and the oxide film sidewalls 8. The nitrogen ions are injected for preventing penetration of boron (B.sup.+) from the P type gate electrode 5a during a heat treatment in a later process.
As shown in FIG. 1g, a third photoresist film 9 is formed on the entire surface of the transistor, except for the P type well 2. Then, N type impurity ions of arsenic (As.sup.+) are heavily injected into both a surface of the exposed P type well 2 and to the N type gate electrode 5a. Next, as shown in FIG. 1h, the third photoresist film 9 is removed, and a fourth photoresist film 10 is formed on the entire surface except for the N type well region 3. P type impurity ions of boron (B.sup.+) are heavily injected into both a surface of the exposed N type well 3 and into the P type gate electrode 5a. Then, the fourth photoresist film 10 is removed, and a heat treatment is conducted at approx. 1000.degree. C. in a nitrogen ambient, to diffuse impurity ions.
The related art method for fabricating an MOS transistor having dual gates has at least the following problems, as shown, for example, in FIG. 2, which illustrates a state of a related art ion injection into a gate electrode.
First, amorphous or columnar silicon is deposited for forming a dual gate electrode. However, a heat treatment in an amorphous state causes depletion in an NMOS region, and the heat treatment of the columnar structure alters device characteristics due to channeling during ion injection. A diffusion speed of the boron in a NMOS region is significantly faster than a diffusion speed of the arsenic in a NMOS region. If the heat treatment is completed long after the injection of arsenic and boron, the boron passes the gate oxide film 4a and invades the substrate 1, which results in channeling. If the time period of the heat treatment is short, the slow diffusion speed of the arsenic in the NMOS region causes depletion of the NMOS region. Moreover, the columnar polysilicon has a preferred orientation in a plane (110) that is very susceptible to channeling during ion injection, while polysilicon, other than amorphous or columnar, has a preferred orientation in a plane (111). In this environment, boron with a smaller ion radius causes channeling which enhances boron penetration during heat treatment and changes characteristics of the device.
Second, as discussed above, nitrogen ions are injected into the gate insulating film 4a before impurity ions are heavily injected into the P type gate electrode 5a. Although penetration of boron injected into the P type gate electrode into regions below the gate insulating film can be prevented during the heat treatment, reduction of an impurity concentration in the N type gate electrode cannot be prevented in the related art approach because arsenic ions injected into the N type gate electrode are outwardly diffused. Accordingly, device characteristics of the NMOS region deteriorate in the related art method.